It is well known that computer memories are prone to occasionally generating "soft" or "transient" errors. Main store memories, which lie external to a microprocessor and store data for extended periods of time, are particularly susceptible to these errors. Secondary level cache memories can also develop soft errors.
Soft errors are typically caused by energetic particles which strike one or more of the semiconductor devices within a memory. Sources of these energetic particles are radioactive decay of packaging materials or cosmic rays. For a more detailed description of the causes of soft errors, and the efforts which have been taken to prevent them, see the U.S. patent application of Miller et al. (Ser. No. 08/603,977 filed Feb. 20, 1996) entitled "Completion Detection as a Means for Improving Alpha Soft-Error Resistance", and the article of C. M. Hsieh, P. C. Murley, and R. R. O'Brien entitled "Dynamics of Charge Collection from Alpha-Particle Tracks in Integrated Circuits". IEEE/PROC. IRPS, pp. 38-42, June 1981. Both of these documents are hereby incorporated by reference for all that they disclose.
As computer systems are very sensitive to the receipt of incorrect data, a single incorrect bit transmitted from memory will frequently lead to a catastrophic system failure (when the data is read and interpreted by a microprocessor). At the very least, the incorrect bit will result in a computer system calculating, displaying or further propagating an incorrect result.
Many modern computer systems provide a means for detecting and correcting soft errors found in external computer memory. While most of these error correction systems are capable of correcting a single erred bit, some may even correct multiple bit errors. Exemplary error correcting codes are discussed in W. Wesley Peterson and E. J. Weldon, Jr.'s, Error-Correcting Codes, 1972, and Shu Lin and Daniel J. Costello, Jr.'s, Error Control Coding--Fundamentals and Applications, 1983. These documents are also incorporated by reference for all that they disclose.
In a computer system comprising error correction hardware, data is read from an external memory array and then immediately processed by the error correction hardware. Corrected data output from the error correction hardware is typically stored in a first level cache memory before being written to a processor's register set. Although the error correction processing time is small, it is encountered each and every time an external memory access is made. In a system performing millions of memory accesses per second, the sum delay attributable to error correction hardware can be substantial.
The number of soft errors encountered can depend on, for example, the size of an external memory array, the amount of time for which data is stored in the array, the altitude at which the array is in operation, or the technology used to build the array. On average, however, soft errors occurring under normal operating conditions are relatively rare--typically occurring maybe once a month.
Given that a modern computer system performs millions of memory accesses per second, and the occurrence of soft errors is relatively rare, one can appreciate that the frequently encountered delay of error correction hardware is a large price to pay for the assurance of accurate data.
It is therefore a primary object of this invention to provide methods and apparatus which opportunistically provide a processor with pre-corrected data, thereby improving microprocessor performance.
It is a further object of this invention to provide methods and apparatus which provide pre-corrected data to a microprocessor, and then, if necessary, flag incorrect data as such prior to its consumption by the microprocessor.
It is an additional object of this invention to provide methods and apparatus which reduce the length of time a processing unit is stalled due to the unavailability of data.